Transfer wafer aided 3D integration

  • Transfer wafer aided bottom-up electroplating technology has been developed for filling high-aspect-ratio TSVs with high quality copper.
  • Transfer wafer also provides device wafer with mechanical support during its ultra-thinning process.
  • Hybrid metal-adhesive bonding is utilized for multiple device layers stacking.
Bottom-up TSV
  • Copper grows from bottom upwards with high directivity during filling process.
  • High quality copper filling capability without forming voids or seams.

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Fabrication Results
  • High-aspect-ratio copper TSVs have been successfully fabricated.
  • Micro metal bumps are fabricated on top of the TSVs by mask-free electroplating.
  • Ultra wafer thinning for concise stacking.
  • A two-layer stacked integration has been demonstrated.
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Chip-to-wafer 3D integration with template alignment

  • A chip-to-wafer (C2W) 3D integration with well-controlled template alignment and wafer-level Cu-Cu bonding has been sucessfully demonstrated.
  • A template is fabricated by etching a thick low-stress polymer layer on the host wafer. The template corner is used as the positioning reference for the precise C2W alignment.
  • C2W stacking is realized by wafer-level bonding Cu-Cu under well-controlled conditions. This novel approach enables precise alignment, few thermal cycles and high throughput of 3D system fabrication.

Fabrication Results
  • Chips aligned and bonded to a host wafer using template alignment and wafer-level Cu-Cu bonding.
  • SEM image of Cu pads for Cu-Cu bonding.
  • Cross-section FIB-SEM images of the bonded interface between the Cu layers on the top chip and the bottom wafer.
  • A Cu daisy chain structure formed by Cu-Cu bonding.
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863 program

National High-tech R&D Program (863 Program)

973 Program

National Basic Research Program of China(973 Program)


National Natural Sicence Foundation of China


Intel Corp.


ABB Corp.


Lam Research Corp.